1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and more particularly, to a structure of a verify circuit for verifying an operation of writing and erasing data in an electrically programmable and erasable nonvolatile semiconductor memory device operable in a page mode which can write data of a plurality of bytes at a time.
2. Description of the the Prior Art
FIG. 1 is a diagram showing a schematic structure of a conventional electrically programmable and erasable nonvolatile semiconductor memory device. In FIG. 1, the conventional electrically programmable and erasable nonvolatile semiconductor memory device (referred to as an EEPROM hereinafter) comprises memory cells 1 arranged in a matrix manner including rows and columns for storing information, an X decoder 3 for decoding a row designating signal (a row address signal) externally generated and selecting a corresponding row selecting signal line (a word line) 2, a Y decoder 5 for decoding a column address signal (a column designating signal) externally generated and selecting a corresponding column selecting signal line (a bit line) 4, data latch circuits 6 for temporalily storing data to be written into the memory cells 1, latch circuits 6a for storing selected control gate lines 20, Y selecting transistors 8 responsive to an output of the Y decoder 5 for connecting the bit line 4 connected thereto to an I/O line 7 serving as a data output line, and sense amplifiers 9 for detecting and amplifying a signal appearing on the I/O line 7. In addition, a control transistor 10 is provided in correspondence to each memory cell to control an operation of writing and erasing data in the memory cell 1.
The memory cell 1 comprises a selecting transistor 12 having a drain connected to the bit line 4, a source connected to a drain of a memory transistor 13 and a gate connected to an output signal line of the X decoder 3, i.e., the word line 2, and the memory transistor 13 having a drain connected to a source of the selecting transistor 12, a source connected to a ground potential and a control gate connected to the control gate line 20 through the control transistor 10. The memory transistor 13 has a floating gate for storing charges.
The control transistor 10 for controlling charge storage operation (writing and erasing of information) of the memory transistor 13 has a source connected to a control gate of the memory transistor 13, a drain connected to the control gate line 20 and a gate connected to the word line 2.
The bit line 4 is connected to the I/O line 7 through the Y selecting transistor 8, and the control gate line 20 is connected to a control line 21 through a Y selecting transistor 8a. An output signal of the Y decoder 5 is transferred to gates of the Y selecting transistors 8 and 8a through a Y gate line 22.
A memory cell 100 of one byte comprises eight memory cells 1 (one byte) connected to each other in parallel and a single control transistor 10 provided in correspondence to the memory cells 1, so that data can be written for each one byte.
The bit line 4 is provided with the data latch circuit 6 and the control gate line 20 is provided with the latch circuit 6a. The latch circuits 6 and 6a are activated in response to a high potential pulse signal V.sub.pp. The latch circuits 6 and 6a output signals at an "L" level when they latch data at an "L" level and generate signals at a high potential V.sub.pp level when they latch a signal at an "H" level.
Operation is now described. In operation of one bit by one bit, description is now made on operation for erasing data of the memory cell 1 (writing of information "1"). In this case, a word line (i.e. a control gate line) 2 selected by the X decoder 3 becomes the high potential V.sub.pp level. The word line 2 is generally provided with a latch circuit (not shown) for further boosting to the high potential V.sub.pp level when the word line 2 is selected to be an "H" level. At that time, a latch circuit connected to a non-selected word line does not operate and outputs a signal which remains at an "L" level. On the other hand, the Y selecting transistors 8 and 8a connected to the Y gate line 22 selected by the Y decoder 5 are turned on, so that the control gate line 2 connected to the selected Y gate line 22 becomes an "H" level through the control line 21. The selected control gate line 2 at an "H" level is further boosted to the high potential V.sub.pp level by the latch circuit 6a. At the same time, the potential on the bit line 4 becomes a ground potential level through the I/O line 7 and the latch circuit 6. In this state, the high potential V.sub. pp is applied to the control gate of the memory transistor 13 through the control transistor 10 and the drain thereof is connected to the bit line 4 at the ground potential through the selecting transistor 12. As a result, electrons are injected from the drain to the floating gate in the memory transistor 13. Accordingly, the threshold voltage of the memory transistor is shifted to a higher level, so that the memory transistor is of an enhancement type. Thus, information "1" is written, that is, the information of the memory cell is erased.
Description is now made on programming, i.e., data writing (writing of information "0"). The potential on the word line 2 selected by the X decoder 3 is boosted to the high potential V.sub.pp level. Then, the Y selecting transistors 8 and 8a connected to the Y gate line 20 selected by the Y decoder 5 are turned on, so that data is written to the latch circuits 6 and 6a. When the data to be written is "0", a signal at an "H " level is transferred to the latch circuit 6a, which transfers a signal at the ground potential level. Then, an output of the Y decoder 5 becomes an "L" level, so that the Y selecting transistors 8 and 8a are turned off. Therefore, a signal at the high potential V.sub.pp level is applied to the bit line 4 to which data is to be written through the latch circuit 6. At that time, since the control gate line 20 is at the ground potential and the selected word line 2 is at the high potential V.sub.pp level, the high potential V.sub.pp is applied to the drain of the memory transistor 13 and the control gate thereof becomes the ground potential level through the control transistor 10. As a result, electrons flow from the floating gate to the drain in the memory transistor 13. Accordingly, the threshold voltage of the memory transistor 13 is shifted to a lower level, so that the memory transistor 13 is of a depletion type. That is, information "0 " is written. More specifically, a program (information "0") is written to the memory cell to which data "0 " is to be written.
In reading out data, the X decoder 3 transfers a signal at an "H" level to the selected word line 2. The Y decoder 5 decodes a column address signal applied thereto and transfers a signal at an "H" level to the corresponding Y gate line 22. The control line 21 is forced to the ground potential level or a predetermined potential level lower than a power supply potential level. At that time, since a signal at an "H" level is transferred to the gates of the Y selecting transistors 8 and 8a connected to the selected Y gate line 22, the Y selecting transistor 8 and 8a are turned on, so that the corresponding bit line 4 is connected to the I/O line 7. When the memory transistor 13 included in the selected memory cell is in an erased state, that is, information "1 " is written so that the memory transistor 13 is of an enhancement type, the memory transistor 13 is turned off, so that no current flows from the I/O line 7 to the bit line 4. On the other hand, when information "0 " is written to the memory transistor 13 in the selected memory cell so that the memory transistor is of a depletion type, the memory transistor 13 is turned on, so that current flows from the I/O line 7 through the bit line 4, the selecting transistor 12 and the memory transistor 13. The sense amplifier 9 provided in correspondence to the I/O line 7 detects whether current flows through the I/O line 7 or not and determines whether information stored in the selected memory cell is "1 " or "0".
The conventional EEPROM has a page mode operation for collectively writing data for a plurality of bytes in order to write data at high speed. In a page mode operation, data are collectively written and erased for memory cells connected to a selected page (a selected single word line).
In a page mode operation, data for bytes selected out of one page to be written are temporalily latched to the latch circuits 6. After the data are latched in the latch circuits 6, data of the memory cells 1 connected to the selected word line 2 are erased and then, the data latched in the latch circuits 6 are collectively written into the corresponding memory cells in response to the high potential signal V.sub.pp.
The conventional nonvolatile semiconductor memory device as described above is not provided with an erasing verify circuit. Therefore, when data are collectively written to a plurality of bytes in a page mode, it is not verified whether a data is surely erased or not before writing data for all the selected bytes, so that the data is liable to be erroneously written.
There is considered another approach in which in a page mode writing operation, after data for the selected bytes out of one page are written and are latched by the latch circuits and then, data of the selected memory cells from one page are erased, it may be verified whether the data have been surely erased or not for the last selected byte out of one page. In this case, it is verified that the data has been erased only for the last selected byte out of one page but not verified that the data has been erased for the other bytes, so that it can not be verified whether all data have been surely erased or not for the selected bytes out of one page.
In an EEPROM which is programmable in a byte mode in which writing is made on byte by byte, a written data verify circuit for detecting whether data is surely written or not is discussed in an article by Lubin Gie et al., entitled "An Enhanced 16K E.sup.2 PROM", IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, 1982, pp. 828-832. However, the prior art does not disclose an erased data verify circuit for detecting whether data is surely erased or not in an EEPROM operable in a page mode.